Projects
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Condor Project Homepage
The goal of the Condor Project is to develop, implement, deploy, and evaluate mechanisms and policies that support High Throughput Computing (HTC) on large collections of distributively owned computing resources. Guided by both the technological and sociological challenges of such a computing environment, the Condor Team has been building software tools that enable ...
  www.cs.wisc.edu/condor/ reviews
The Stanford FLASH Project
Welcome to the FLASH Home Page What's new (most recent: 03/11/98) This site provides information about the design of the FLASH (FLexible Architecture for SHared memory) multiprocessor and about related work here at Stanford. The FLASH machine is being developed in partnership with the Information Technology Office in ARPA, with LSI Logic, and with significant cooperation from MIPS Technologies.
www-flash.stanford.edu/ reviews
Project AppleSeed
Do It Yourself FAQ Publicity Other Clusters Benchmarks Technical Reports Scientific Results High Schools Personal Parallel Computing Plug and Play Parallel Processing For Mac OS 9 and later: (Click for Mac OS 8.6 and earlier) How to Build an AppleSeed a one-page recipe for constructing a Macintosh cluster Recommended software (what we use to keep 'em running): Most innovative commercial software ...
exodus.physics.ucla.edu/appleseed/appleseed.html reviews
Parallel I/O Archive at Dartmouth
Parallel I/O Archive This archive contains information about parallel I/O research. Most of the coverage relates to parallel file I/O. Unfortunately I have not had the time to keep it updated in the past few years. Many links are no doubt broken. European users please note there is a mirror site (sort of). What's new Key resources: People in the field Parallel I/O bibliography Dictionary on ...
www.cs.dartmouth.edu/pario/ reviews
MIT Alewife Project: Home Page
MIT Alewife Project: Home Page Alewife is a large-scale multiprocessor that integrates both cache-coherent, distributed shared memory and user-level message-passing in a single integrated hardware framework. Each Alewife node consists of a 33 MHz Sparcle integer unit, an off-the-shelf FPU, 64 kbytes of direct-mapped cache, and 4 Mbytes of globally-shared main memory. The nodes communicate via ...
 www.cag.lcs.mit.edu/alewife/ reviews
Avalanche Scalable Parallel Processor Project
University of Utah Department of Computer Science The goal of the Avalanche project is to enable the construction of usable and truly scalable parallel computing platforms that are not exorbitantly expensive, yet are still capable of achieving peta-op performance levels. Low communication latency is the key to achieving performance scalability for both of the common parallel computation models, ...
www.cs.utah.edu/avalanche/ reviews
Distributed Systems Laboratory
Distributed Systems Laboratory Argonne National Laboratory University of Chicago The Distributed Systems Laboratory (DSL) is a research and software development group within the Mathematics and Computer Science (MCS) Division at Argonne National Laboratory and the Department of Computer Science at The University of Chicago. A Grid is a persistent infrastructure that supports ...
www-fp.mcs.anl.gov/dsl/index.html reviews
Wisconsin Multifacet Project
Wisconsin Multifacet Project UW-Madison Computer Architecture Group Department of Computer Sciences University of Wisconsin-Madison Directed by Mark Hill & David Wood Overview People Publications Theses Related Projects Links Overview The Wisconsin Multifacet Project proposes to perform research to improve the multiprocessor servers that form the computational infrastructure for Internet web ...
www.cs.wisc.edu/multifacet/ reviews
The D System Home Page
Welcome to the World Wide Web home page for the D System, a research project of the Parallel Programming Systems group at Rice University. Objective We are conducting research into program analysis, code generation, and programming tools for data-parallel languages like High Performance Fortran. If this research is successful, computational scientists and engineers will be able to write ...
www.cs.rice.edu/~dsystem/ reviews
QUID
Complex Parallel Architectures Deep Memory Hierarchy Hybrid Memory Model Questions What is QUID Positions Available QUID Community Join QUID QUID Forum Download Codes Toolbox Compilers Debuggers Perf. Analyzers The Toolbox Events WOMPEI 2002 ICS'02 Presentation Material Papers Talks People QUID team Collaborators Contact Us Links Related Research Case Studies Documentation HPC Centers QUID ...
 www.lri.fr/~gk/QUID/ reviews
Design of Open Engineering Systems Research Lab Homepage
Laboratory for the Design of Open Engineering Systems (DOES)Department of Mechanical Engineering , University at Buffalo. The DOES lab strives to find and develop fundamental scientific principles in design and to facilitate their application in practice and education. Our focus is on open engineering systems - those systems that change and evolve over time due to changes in ...
does.eng.buffalo.edu/ reviews
Scott Schnoll's Microsoft Cluster Server Center
Scott Schnoll's Microsoft Cluster Server Center is the ultimate source for Microsoft Cluster Service, Windows 2000 Cluster Service and Network Load Balancing information and answers.
www.nwnetworks.com/cluster.html reviews
RASSP
Quad Charts VHDL Taxonomy Document RASSP Legacy Application Notes and Case Studies Papers Shows Video RASSP Educator/ Facilitator For more information: jsaultz@atl.lmco.com ...
www.atl.external.lmco.com/projects/rassp/rassp.html reviews
Purdue's Adapter for Parallel Execution and Rapid Synchronization: The TTL_PAPERS Design
Purdue's Adapter for Parallel Execution and Rapid Synchronization: The TTL_PAPERS Design H. G. Dietz, T. M. Chung, T. Mattox, and T. Muhammad School of Electrical Engineering Purdue University West Lafayette, IN 47907-1285 hankd@ecn.purdue.edu January 1995 Abstract Tightly-coupled parallel machines are being replaced with clusters of workstations connected by communication networks yielding ...
 aggregate.org/TechPub/ICPP95/icpp95.html reviews
Communication
Virtual memory-mapped communication (VMMC) was developed out of the need for a basic multicomputer communication mechanism with extremely low latency and high bandwidth. This is achieved by allowing applications to transfer data directly between two virtual memory address spaces over the network. The basic mechanism is designed to efficiently support applications and common communication models ...
www.cs.princeton.edu/shrimp/html/communication.html reviews
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 math.nist.gov/cgi-bin/savgfwd/ reviews
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